a techfocus media publication :: April 1, 2008 :: volume XI, no. 01

FROM THE EDITOR

This week, MIPS announced the industry’s first multi-core, multi-threaded processor IP – their new MIPS32 1004K. Following on their super-fast 74K core announced last year, 1004K boosts throughput even more without a big power penalty by taking advantage of a multi-core architecture. Our latest feature has the details.

Also, in the spirit of the day, if you aren’t yet solid on the whole multi-core recipe, Bryon Moyer lays out the details of multi-processing.  While parallelism may seem confusing at first, as Bryon explains, it really can be easy as pie.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@embeddedtechjournal.com. If you'd rather sound off in public, please post your comments or questions in our new Journal Forums.

Kevin Morris – Editor-in-Chief
Techfocus Media, Inc.

EVENTS and ANNOUNCEMENTS

New Tektronix Webinar: Efficiently Triggering, Debugging and Decoding Low-Speed Serial Buses. Learn  how industries are facing key technical challenges in RS-232, I2C, SPI and CAN bus design. Become an expert today. Click here

Powering FPGA-Based Systems … Simply
DC/DC µModuleTM regulators are complete system-in-package power supplies, ready to power your FPGA-based systems. These powerful DC/DC circuits include the inductor and MOSFETs and are simplified to resemble an IC. From low to high power, these DC/DC µModule systems are backed by Linear Technology’s rigorous testing.
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High Efficiency Power Supply Design for FPGA-Based Systems. Performance of FPGA-based systems depends on the electrical and thermal performance of DC/DC regulators. A properly packaged power management device improves regulation accuracy and stability while removing heat quickly. DC/DC µModuleTM regulators from Linear Technology are complete system-in-package power supplies in an IC form-factor with optimum layout and very low thermal impedance.
Click here for more

Xilinx Virtex(r) -5 FPGA Development kit for PCIe(r)
Cut design time, power and cost with built-in PCIe block.
Get started now with this PCI-SIG compliant solution from Xilinx.
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Mixed-Signal ASICs from ChipX

  1. USB 2.0 & PCI Express ASIC Designs and FPGA conversion
  2. USB-IF & PCI-SIG certified ASICs
  3. Standard Cell, Hybrid ASIC and Structured ASIC solutions
  4. Low NRE, fast Time to Market, USB & PCIe ASIC platforms

Win a PCIe Development Board click here

Understanding the cost and time restraints of the industry, PDI provides the perfect low maintenance out source solution for the production and shipping of your training manuals globally.  Through on-line ordering, version control, global coverage with localized production, efficiencies will be gained and costs controlled.
Find out more at www.pdi-europe.com

NEW!! IC Journal - Do you love Embedded Tech Journal? We're happy to announce our new IC Design and Verification Journal.  It'll be just like Embedded Tech Journal except, you know, about ASICs and stuff. 
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LATEST NEWS

April 1, 2008

MIPS Technologies Unveils Industry's First Multi-threaded, Multiprocessor IP Core for the Embedded Market

Leading Embedded Engineers to Discover New Design Techniques at Microchip Technology’s 12th Annual Worldwide MASTERs Conference

Beceem Introduces World’s First Single-Chip, 65 Nanometer Mobile WiMAX Solution – Sets New Standard for Low Power Consumption

Magnum Semiconductor Licenses Sidense’s Logic Non-Volatile Memory for Consumer Entertainment Products

Sound Design Technologies Launches VOYAGEURIITM Audio Processing DSP Platform

VirtualLogix™ Expands Real-Time Virtualization Solution to Include Windows® Environments

March 31, 2008

Imperas to Demonstrate OVP During This Week’s Multicore Expo

IMEC Offers Three Up-to-date Engineering Courses: CMOS Plasma Etching, SOI, and Sub-90nm Si Processing

Express Logic and IAR Systems Team Up to Provide
ThreadX® RTOS Support in IAR Embedded Workbench® IDE for Freescale ColdFire®

March 28, 2008

InterNiche Technologies Releases v3.1 of its Embedded Protocol and Announces Availability of RTP/RTCP and SNTP Modules

New PSoC® Textbook Addresses the Basics of Mixed-Signal Embedded Design

NEC LCD Technologies Announces New 7.0-inch Wide-Format LCD Modules Featuring White LED Backlight System

March 27, 2008

Linux Professional Institute to Develop Enterprise-level "Security" Exam

ENlight UK Ltd launches Small Form Factor

VMETRO Adds Quad-Core Processing Engine and Single Board Computer to 6U VPX Offerings

March 26, 2008

NXP Semiconductors introduces four new 32-bit ARM9 microcontrollers

CURRENT FEATURE ARTICLES

MIPS Moves on Multi-Core
MIPS32 1004K (Kevin Morris)
As Easy As Pie
(Bryon Moyer)

Embedded World
(Dick Selwood)
Bringing Reality to PCB Design
by Rob Irwin, Altium Limited
Seeding Multicore Infrastructure
Imperas Launches Open Virtual Platforms
(Bryon Moyer)
Better Mobile Media
QuickLogic Offers VEE (Kevin Morris)
Multicore to Massively Parallel
(Dick Selwood)

JOURNAL WEBCASTS

NEW!! CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age-DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK CES 2008. Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now.

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier. Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)


CHALK
TALK
Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)


MIPS Moves on Multi-Core
MIPS32 1004K (Kevin Morris)

At first, the concept of “multi-core” from a processor IP company might seem a bit confusing.  Couldn’t we already put multiple MIPS cores on our devices?  If your concept of multi-core ends with putting more than one processor on a chip, you may not be yet dialed into the subtleties.

This week, MIPS launched their highest-performance solution ever with the new MIPS32 1004K “Coherent Processing System” – a multi-core, multi-threaded IP solution.  The challenge of keeping all your cores busy in a symmetric multi-processing (SMP) system is actually made much easier when the multi-processor is combined with multi-threading.  With monolithic processors continuing to pound frequency and particularly power consumption walls, multi-core technology is permeating every segment of computing.  Embedded applications have long taken advantage of multiple processors – tasking different cores to perform completely independent system functions.  More general multi-core processing is relatively new, however, and the proliferation of higher-end applications running on sophisticated operating systems makes multi-core an imperative for power-sensitive, performance-hungry embedded applications.

Last year, MIPS rolled out their highest-performance monolithic, single-threaded core – the MIPS32 74K.  The 74K gets its performance the old fashioned ways – higher frequencies (up to 1GHz) and deeper, more sophisticated pipelines.  This approach, however, runs into power problems as you continue to boost your performance.  When processes can be efficiently parallelized, multiple cores can do the same work at lower frequencies or more work at the same frequencies with much better power-per-performance metrics.  For those applications, MIPS is now rolling out the 1004K.  [more]


As Easy As Pie
(Bryon Moyer)


ANNOUNCER: It’s spring, the harvest is and holidays are behind us, and the apples in cold storage are starting to age. Someone needs to come to their rescue before it’s too late. And that can mean only one thing here in Kitchen Stadium: it’s Time for Pie. So today’s challenge will be an homage to Mom’s apple pie.

But things are going to work a little differently this time out. Instead of a challenger taking on one of the Iron Chefs, five Iron Chefs will battle each other. Half of the points awarded will be for quality – taste, execution, and presentation – but half will be awarded by number of pies made. Each chef can have a team of assistants, but due to the available space, each team is limited to five people.

Now it appears that the teams have all been organized differently, so as the battle gets underway here, we’ll take a look at the different strategies each team has for mastering the challenge.

Let’s start with team 1.These guys seem to have set things up pretty simply: each team member will make pies independently of all the others, and just keep going until the time is up. Each member starts with apples from the bushels and spices and flour from bins, and ultimately delivers a pie to the judging table.

COMMENTATOR: So that means that all of the team members have to know how to make an entire pie! They’ve had to bring in some heavyweights that can handle all the duties. And you know, the more skills they have, the more they tend to be, shall we say, prima donnas, and get harder to work with. [more]

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