FROM
THE EDITOR
This week, MIPS announced the industry’s first multi-core, multi-threaded processor IP – their new MIPS32 1004K. Following on their super-fast 74K core announced last year, 1004K boosts throughput even more without a big power penalty by taking advantage of a multi-core architecture. Our latest feature has the details.
Also, in the spirit of the day, if you aren’t yet solid on the whole multi-core recipe, Bryon Moyer lays out the details of multi-processing. While parallelism may seem confusing at first, as Bryon explains, it really can be easy as pie.
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Kevin
Morris – Editor-in-Chief
Techfocus Media, Inc.
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MIPS Moves on Multi-Core
MIPS32 1004K (Kevin Morris)
At first, the concept of “multi-core” from a processor IP company might seem a bit confusing. Couldn’t we already put multiple MIPS cores on our devices? If your concept of multi-core ends with putting more than one processor on a chip, you may not be yet dialed into the subtleties.
This week, MIPS launched their highest-performance solution ever with the new MIPS32 1004K “Coherent Processing System” – a multi-core, multi-threaded IP solution. The challenge of keeping all your cores busy in a symmetric multi-processing (SMP) system is actually made much easier when the multi-processor is combined with multi-threading. With monolithic processors continuing to pound frequency and particularly power consumption walls, multi-core technology is permeating every segment of computing. Embedded applications have long taken advantage of multiple processors – tasking different cores to perform completely independent system functions. More general multi-core processing is relatively new, however, and the proliferation of higher-end applications running on sophisticated operating systems makes multi-core an imperative for power-sensitive, performance-hungry embedded applications.
Last year, MIPS rolled out their highest-performance monolithic, single-threaded core – the MIPS32 74K. The 74K gets its performance the old fashioned ways – higher frequencies (up to 1GHz) and deeper, more sophisticated pipelines. This approach, however, runs into power problems as you continue to boost your performance. When processes can be efficiently parallelized, multiple cores can do the same work at lower frequencies or more work at the same frequencies with much better power-per-performance metrics. For those applications, MIPS is now rolling out the 1004K. [more]
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As Easy As Pie
(Bryon Moyer)
ANNOUNCER: It’s spring, the harvest is and holidays are behind us, and the apples in cold storage are starting to age. Someone needs to come to their rescue before it’s too late. And that can mean only one thing here in Kitchen Stadium: it’s Time for Pie. So today’s challenge will be an homage to Mom’s apple pie.
But things are going to work a little differently this time out. Instead of a challenger taking on one of the Iron Chefs, five Iron Chefs will battle each other. Half of the points awarded will be for quality – taste, execution, and presentation – but half will be awarded by number of pies made. Each chef can have a team of assistants, but due to the available space, each team is limited to five people.
Now it appears that the teams have all been organized differently, so as the battle gets underway here, we’ll take a look at the different strategies each team has for mastering the challenge.
Let’s start with team 1.These guys seem to have set things up pretty simply: each team member will make pies independently of all the others, and just keep going until the time is up. Each member starts with apples from the bushels and spices and flour from bins, and ultimately delivers a pie to the judging table.
COMMENTATOR: So that means that all of the team members have to know how to make an entire pie! They’ve had to bring in some heavyweights that can handle all the duties. And you know, the more skills they have, the more they tend to be, shall we say, prima donnas, and get harder to work with. [more]
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