a techfocus media publication :: January 29, 2008 :: volume X, no. 04

FROM THE EDITOR

This week, European editor Dick Selwood is back with tales from the Euro-IP front.  The re-use of IP blocks, from processor cores to high-speed I/O - is a hot topic in European circles this month. The latest feature article from our intrepid investigator has the details.

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LATEST NEWS

Janary 29, 2008

Lattice and Praesum Communications Deliver Low-Cost Serial RapidIO Solutions

The Ethernet Alliance® Demonstrates Backplane Ethernet at DesignCon 2008

Freescale Stretches Boundaries of Energy Efficiency with Ultra-Low-Power 8-Bit Microcontrollers

Intermec Introduces Windows Mobile®-Based CK61ex Handheld Computer, the Most Fully-Featured Near-Far EX Imaging Technology Product Yet

January 28, 2008

Sybase iAnywhere Announces SDK Support for Latest Bluetooth Wireless Specification

Actel Announces Availability of MIL-STD 883 Class B Qualified Four-Million Gate RTAX4000S

Xilinx Launches New XtremeDSP Development Tools Package and XtremeDSP Development Kit

MosChip Launches PCIe to Peripheral I/O Controller with Support for Serial, Parallel, ISA and USB Interfaces and Standards

January 24, 2008

Nascentric Unveils Omegasim - Its Next Generation Mixed Analog/Digital Fast-SPICE Simulator

Reqtify Version 3.1 to debut at Embedded World 2008

VIA Unveils Next-Generation Isaiah x86 Processor Architecture

Mistral announces availability of New Rugged Low-Power Quad-Core VME DSP Engine from Curtiss-Wright

January 23, 2008

ARM Achieves 10 Billion Processor Milestone

Japan's University of Tsukuba Selects Appro Xtreme-X Supercomputers for Next Generation High Performance Computing

IAR Systems partners with System Semiconductor on motion controller developer’s kit

Jazz Semiconductor Announces Avnera Utilized Its 0.18-Micron RFCMOS Process for Breakthrough Wireless Music and Voice Chips

V.i. Labs Enhances CodeArmor to Meet Growing Enterprise and Software Vendor Needs for Intellectual Property, Reverse Engineering, and Anti-Piracy Protection


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CURRENT FEATURE ARTICLES

IP - European Style
by Dick Selwood, Embedded Technology Journal
Platformification
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What’s a CSSP?
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The Need for Safe and Secure Software... It’s About Time!
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Embedded Everything
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The Countess, the Moon and a Barbecue
Ada Comes to Eclipse
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JOURNAL WEBCASTS

NEW!! CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier - Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

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CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

CHALK TALK Did you miss the ARM Developers' Conference?  Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Xilinx Virtex-5 Power Optimization & Power Design Guidelines (Xilinx)

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Addressing Size, Weight, and Power Constraints (Altera)

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IP - European Style
by Dick Selwood, Embedded Technology Journal

IP07 was the tenth meeting in Grenoble of IP providers and users under the umbrella of Design and Reuse (www.designandreuse.com), the IP portal. Europe editor Dick Selwood compares facts and marketing-speak.

It sounds like the start of a joke. “There were three processor manufacturers at a conference….” And when the three processor manufacturers were asked, “What is needed to service the power- conscious emerging mobile video marketplace?” they came up with three similar answers. The man from MIPS said that it would be serviced by the ecosystem that has developed around a MIPS architecture with added analog capability from Chipidea, their recent acquisition. The man from ARC said that the true path forward was a reconfigurable, heterogeneous multiprocessor architecture, and there was a family of ARC video sub-systems to prove it. And the man from SiliconHive said that the true way is a coupled massively-parallel architecture with a parallelising compiler, and here is the starting point, the VSP2000 family. The chairman of the panel session was from Cadence, and he said that, whatever the solution, it would need EDA tools that were power-aware.

In fact there was more commonality than a joke might suggest. They all agreed that the power requirements of mobile video – and mobile video was chosen as currently the most processor-intensive and therefore the most power-demanding mobile application - were going to be solved only by a holistic approach, starting with an analysis of the functionality of the device, what it would be doing, and what bits would need to work with other bits for specific tasks. From this it should be possible to build an architectural model to explore different trade-offs and undertake power analysis. The end product could then be designed so that applications would run only those sections that are needed, powering down the rest. True, different trade offs, such as process technologies, clock gating, and software designed for lower power would also help, but the key has to be to look at the high level of the system. [more]


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