FROM
THE EDITOR
This week, we come to you from the Design Automation Conference (DAC) in San Francisco, California. DAC is charting the changes in the electronic design automation (EDA) industry as the design tool business splits its energy into two divergent streams - pursuit of more exotic, smaller-geometry digital IC design, and management of the exploding complexity of high-level hardware/software system design. Our newest feature article tackles these trends and offers you our analysis.
Our Journal Jobs website is sporting new
features, new jobs, and a host of new opportunities for employers and job seekers alike. If you
haven’t visited www.journaljobs.com
lately, stop by and see what’s cooking in the world of technology employment.
Thanks
for reading! If
there's anything we can do to make our publications
more useful to you, please let us know at: comments@embeddedtechjournal.com
Kevin
Morris – Editor
Embedded Technology Journal
|
ANNOUNCEMENTS
The Xilinx Virtex-5 family is the world’s first 65nm
FPGA.
Built on the revolutionary ExpressFabric
architecture, it is the ultimate system integration
platform, delivering unmatched performance, ultimate
connectivity, optimized power, and the lowest system
cost. The Virtex-5 family offers four platforms, each
with an optimized balance of capabilities and on-chip
resources Avnet is offering qualified registrants a FREE
Virtex-5 Data Book on CD.
 Request your copy today
|
FPGA AND STRUCTURED ASIC JOURNAL
A weekly e-mail newsletter from techfocus media (publishers of Embedded Technology Journal) dedicated to the design and application of FPGA and structured ASIC technology.
 SUBSCRIBE NOW - FREE!
|
|
JOURNAL WEBCASTS
JOURNAL WEBCASTS ON DEMAND:
"Designing 2Gbps Parallel I/O with the LatticeSC FPGA" sponsored by Lattice Semiconductor
 Click here to watch!
Lattice's new 90nm LatticeSC family--general introduction, sponsored by Lattice Semiconductor.
 Click here to watch! |
|
|
Electronic Elitism
DAC Divulges Design Tool Dilemmas
The 43rd annual Design Automation Conference (DAC) got underway yesterday in San Francisco,
California. The technical sessions have begun, the exhibits are open, and the parties, PowerPoints and pejoratives have now
commenced. Last night, at a media, analyst, and customer briefing dinner at the San Francisco Museum of Modern Art, Walden Rhines,
Chairman and CEO, hosted a customer presentation explaining how Mentor's new Caliber nmDRC accelerates nanometer design rule
checking by "hyperscaling" – a technique that takes efficient advantage of multiple processing elements to deliver many times
the previous performance in giant DRC runs.
Beyond promoting the polygon-pushing power of parallel processing, Mentor's presentation also highlighted an
interesting reality of today's Electronic Design Automation (EDA) industry – nanometer class design tools are getting bigger,
faster, more sophisticated, more expensive, and consequently, more exclusive. Among the customers heaping praises on Caliber nmDRC
for its parallelizing prowess were AMD and Intel – hardly the novice class in semiconductor design.
It is no secret that the number of ASIC and COT (customer-owned tooling) design starts has declined steadily over
the past several years and is forecast to continue declining for the foreseeable future. Along with the decline in the number of
design starts, the number of companies and designers engaged in ASIC/COT design has declined as well. At the same time, the cost
and complexity of ASIC/COT design and the sophistication of the tools and methods required to complete a current-generation chip
has risen almost exponentially. [more]
|
|
