Source: IMEC
March 31, 2008

IMEC Offers Three Up-to-date Engineering Courses: CMOS Plasma Etching,
SOI, and Sub-90nm Si Processing

Leuven, Belgium, April 2008 --- IMEC, the leading European Research
Center on advanced micro- and nanoelectronics technologies and systems,
again offers its proven two- and three-day high-level courses directed
at engineers and technicians, managers and executives with
responsibility in process development, and support, process integration
and device design as well as chip manufacturing, metrology and materials
research, marketing and sales. The courses are held during May and June
2008 and taught by internationally renowned academic researchers at
IMEC's facilities in Leuven.

Plasma Etching for CMOS Technology and ULSI Applications (May13 to 15) This course is directed at engineers and technicians as well as other
industry officials who need a deeper understanding of the performance
and limitations of plasma processes for CMOS applications and ULSI. It
covers fundamental and practical aspects of front-end and back-end
processes for deep submicron CMOS. The emphasis is on real-world
problems in manufacturing, integration and device scaling. Day 1 covers
the fundamentals, passivation layers, etch mechanisms in halogen-based
plasmas, mass spectrometry analyses, monitoring chamber walls coating,
micro-trenching and other pertinent issues. Day 2 handles gate etching
strategy and chemistry, Si mask material, thin-gate oxide behavior,
resist trimming, dual-doped gates, soft landing steps, metal gate
etching, high-k etching, shallow-trench isolation, passivation Layers on
STI sidewalls, and more. Day 3 deals with oxide and low-k etching,
fluorocarbon film thickness measurement, dual hard mask strategies, and
the impact of ashing plasmas and chemistries on low-k material
modifications.

SOI technologies for analog, digital and RF SOCs
and microsystems applications (May 15 and 16)
This two-day course addresses advanced SOI issues in low-voltage,
low-power CMOS systems-on-chip, with emphasis on analog and microwave
functions, from basic technology and device levels to original circuit
studies, demonstrating properties and performance of SOI being
significantly superior to those of bulk CMOS. Covered is a large span of
processes, from submicron CMOS for pure analog to advanced multiple-gate
deca-nanometer CMOS for systems-on-chip. Day 2 will examine bulk and
surface micro-machined SOI MEMS and report on recent SOI developments of
thin three-dimensional (3-D) released micro-sensors (temperature, flow,
magnetic) and thin dielectric membranes (flow, gas, pressure), as well
as micro-machines implementing new experimental tools to probe
mechanical responses at very small scales.

Silicon processing for Sub-90nm circuit fabrication (June 11 to 13) This three-day course targets engineers, managers and executives in
process development, support and integration, device design and
manufacturing, materials, marketing and sales. It is a state-of-the-art
training program focusing on advanced deep sub-micron devices. Day 2
will be dedicated to business managers' approaches to design flow,
high-level specification, system design, synthesis, verification, timing
closure, layout generation, cell-libraries, IP-blocks, verification,
test pattern generation, GDSII-layers, reticles, alignment, defect
density, yield, cost, etc. CMOS scaling problems pertinent to the 90nm
node are discussed, and an outlook towards 45nm and lower is given. The
course covers a methodology for yielding products and ramping up
production while considering the power-performance trade-off as a
fundamental limiter.

Also on the course agenda:
Co-implantation of Ge and F, solid-phase epitaxial regrowth (SPER),
flash or laser annealing techniques, strained silicon, exposure systems
such as i-line and deep-UV (248, 193 nm), photoresists, phase-shift
masks, off-axis illumination, optical proximity correction, immersion,
EUV, double patterning and post-optical lithography,. Day 3 covers
contact metallization and metal CMP, advances in on-chip interconnect,
damascene and low-k, as well as key process integration and
manufacturing. Mass-produced multi-Gbit flash memory in 56nm technology
is covered including an overview of basic mechanisms.

For detailed course descriptions and price information, please go to:

Plasma Etching (May 13 -- 15): www.imec.be/mtc/PlasmaEtching.htm

SOI (May 15 and 16):
www.imec.be/mtc/SOI.htm

Silicon Processing (June 11 to 13): http://www.imec.be/mtc/SiliconProcessing.htm

To register or for more information mail to: training@imec.be

About IMEC
IMEC is a world-leading independent research centre in nanoelectronics
and nanotechnology. Its research focuses on the next generations of
chips and systems, and on the enabling technologies for ambient
intelligence. IMEC's research bridges the gap between fundamental
research at universities and technology development in industry. Its
unique balance of processing and system know-how, intellectual property
portfolio, state-of-the-art infrastructure and its strong network of
companies, universities and research institutes worldwide position IMEC
as a key partner for shaping technologies for future systems.

CONTACT:
Katrien Marent, Director of External Communications, IMEC, T: +32 16 28
18 80, katrien.marent@imec.be