Jasper Design Automation Highlights ‘Low-Effort, High-Leverage’ Formal Verification at DAC 2007

Verification Experts Lawrence Loh and Rajeev Ranjan Share Their Insights on DAC Panels Discussing Formal Deployment and Verification Coverage

Mountain View, Calif. – May 30, 2007 – Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced it will highlight ‘low effort, high-leverage’ formal verification solutions at this year’s Design Automation Conference (DAC) in San Diego, California, June 4-7, 2007. ‘Low-effort, high-leverage’ formal is made possible with the introduction of JasperGold Verification System v4.3 and GamePlan™ Verification Planner v1.1, both announced earlier this year. JasperGold Verification System - featuring Jasper Lossless Abstractions™, Proof Accelerators™ and Formal Scoreboard™ capabilities - enables high-level verification while simultaneously simplifying the user experience. The increased performance, ease-of-use, modeling and design analysis features of JasperGold Verification System were designed to meet the needs of both novice and advanced users of formal verification, as well as design engineers with no formal experience.

See Demonstrations of JasperGold and GamePlan at DAC booth #2853

Demonstrations of JasperGold® Verification System, and GamePlan™ Verification Planner will be available during exhibit hours, Monday through Thursday, at Jasper Design Automation’s DAC booth #2853.

Requests for private appointments in Jasper’s demo suite may be booked in advance of the show by visiting http://www.jasper-da.com/events/DAC2007/private_demo.htm or sending email to info@jasper-da.com. To arrange an appointment by telephone, please call +1.650.966.0245.

Free Mini-Seminars

Jasper’s formal verification experts will be presenting two free 45-minute mini-seminars at DAC. The first of these is entitled “Low Effort, High Leverage Formal”, and will cover methods using JasperGold to achieve high-level proofs with minimal effort, thereby maximizing the leverage from formal verification.

The second seminar, entitled “Deploying Formal”, will present a production-proven method to integrate both “light formal” and “deep formal” methodologies into an exiting simulation-based verification flow, in order to improve both verification productivity and completeness.

To view further seminar details and to reserve your seat, visit: http://www.jasper-da.com/events/DAC2007/mini_seminar.htm

Verification Panels at DAC

At this year’s DAC, the conference will feature two panels focused on addressing key verification issues: formal verification deployment, and verification coverage.

The first of these panels, entitled, “Deploying Formal: When and Where?” will be held on Tuesday, June 5th, from 2:00 – 3:00 p.m., at the Pavilion stage, booth #6360. Lawrence Loh, Director of Applications Engineering at Jasper, will join panelists from Cisco and NVIDIA to discuss the advantages gained by understanding the types of design best suited for formal verification, and where in the flow this technology should be applied for optimal results.

The second, entitled, “Verification Coverage: When is Enough, Enough?”, will be held in room 6A on Thursday, June 7th, from 9:00 a.m. to 11:00 a.m. Rajeev Ranjan, Jasper’s CTO, will join other panelists from Cadence, Hewlett-Packard, IBM, Mentor Graphics, and Sun Microsystems to debate how to combine coverage between different tools and technologies – such as constraint-driven random simulation, directed testing, formal verification and hardware acceleration - to gain an understanding of overall verification completeness. Panelists will explore possible solutions for handling all the available data and abstracting it into actionable metrics, as well as discuss the industry’s progress in defining a coverage interoperability standard.

About Jasper Design Automation

Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company’s flagship product, JasperGold Verification System, is the first verification product to deliver complete “deep formal” systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold Express, Jasper’s formal ABV solution, provides the industry’s leading “light formal” solution, complementing simulation-based approaches by accelerating bug hunting as well as coverage attainment. The JasperGold family quickly isolates bugs with a fast, static debugging capability, and then proves the absence of bugs, trimming design schedules. For further details on how to ensure guaranteed correctness where it matters most, please visit http://www.jasper-da.com.

Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan and InFormal are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.