CriticalBlue Announces Multicore Methodology for Single Threaded Software

Cascade Coprocessor Synthesis Enhanced to Implement Multicore Platforms

San Jose, California – May 14, 2007 – CriticalBlue, a provider of tools for accelerating software in embedded microprocessor applications, today has announced that it has added multicore development capability to its customer-proven Cascade coprocessor synthesis solution. The company’s programmable coprocessor methodology enables multicore platform design while eliminating the need to redevelop applications software to use multiple threads, a time-consuming task with testability and reliability challenges and difficult-to-predict performance outcomes.
“Multicore is not new, but its deployment is going through exponential growth. Primarily, this is being driven by today’s power consumption constraints requiring concurrency to be exploited at all levels and, together with the dominance of product functionality in software requiring high-performance programmable engines, it is clear that system complexities have outgrown manual multicore methodologies,” said David Stewart, chief executive officer of CriticalBlue. “By engaging with customers and specifically noting the importance of legacy software and associated development techniques, it became obvious to us that what the market needs is a pragmatic multicore methodology, and that our revolutionary synthesis and analysis technology can deliver it.”

Optimizing Multicore Implementation of Single-Threaded Software
CriticalBlue’s multicore methodology uses Cascade’s profile-driven approach, delivering a pragmatic and incremental solution for end users. The key elements of the flow are:

 Starting point of standard C/C++ single threaded code with no language restrictions or extensions

 Analysis environment which allows developers to identify performance bottlenecks in the code, together with any dependencies that inhibit task-level parallelism

 Dependency visualization, which helps guide the developer toward code re-factorings to optimize multicore performance and power consumption

 Refactored code which is ‘multicore ready’ but still unrestricted C/C++ code

 Multicore mapping capability for developers to target blocks of software functionality onto particular coprocessors

 Multicore coprocessor synthesis using existing Cascade synthesis technology to meet performance and power requirements

 Multicore communication synthesis which creates an efficient, direct inter-coprocessor communication infrastructure, minimizing memory contention and system bus bottlenecks

In embedded system operation, the existing processor resources execute their assigned software tasks in their normal manner, while the multicore coprocessor array autonomously executes parallel tasks, with all data dependencies correctly observed.

CriticalBlue’s Cascade multicore methodology enables the development of an array of automatically-synthesized, coordinated, application-optimized programmable coprocessors, each of which executes parallel tasks extracted from the original single-threaded software description. The programmable multicore array – together with existing processing resources such as general purpose processors and DSPs – enables a balanced, optimized distribution of software tasks that meets the system’s performance and power consumption targets. It also reduces – or even eliminates – the need for custom fixed-function hardware accelerators.

Individual Cascade coprocessors can be synthesized for multiple processing tasks, and the array can be readily reprogrammed with new and updated software tasks as the target applications evolve to address new market needs. The CriticalBlue multicore methodology thus significantly eases and speeds both new and derivative design.

CriticalBlue and Synopsys at DAC 2007
CriticalBlue will demonstrate its latest Cascade release, Cascade 2.4, showing the automated application software-driven coprocessor development flow and its integration with Synopsys tools and DesignWare® IP. The demonstration shows in-system verification of Cascade-synthesized coprocessors within a realistic subsystem. The subsystem, built using Synopsys’ DesignWare IP for the ARM® AMBA® protocols is rapidly assembled utilizing the Synopsys core Assembler, automated assembly tool.

According to Michael Posner, product manager of DesignWare IP Solutions for the AMBA protocols at Synopsys, “The demonstration shows that CriticalBlue's Cascade application-optimized coprocessors can be rapidly integrated into a fully functional subsystem with Synopsys' DesignWare IP and coreAssembler, using the IP-XACT™ specification, thus enabling an automated multi-vendor knowledge-based IP design and verification flow.

Specific new features contained in the Cascade 2.4 release include:
ARM v6 ISA support: Full support of SIMD and other ARM v6 instruction extensions that increase coprocessor performance for suitably optimized embedded software
Profile timeline view: Enhanced visualization enabling the developer to understand the application software execution flow to identify further possible optimizations
Linkable microcode support: Linking support to ease the deployment of Cascade coprocessor microcode as a reusable and reprogrammable IP block.

Quality of result improvements: Continued performance and area improvements and improved microcode density

Spirit IP-XACT support: Standardized IP descriptions for simplified import of Cascade coprocessors into IP assembly and SoC design and verification environments

CriticalBlue and Fujitsu at DAC 2007
CriticalBlue will demonstrate the execution of an MP3 decoder algorithm in a low power MP3 audio system running on a Fujitsu prototype development board containing an ARM9™ processor and a Xilinx Virtex™-2 FPGA. Starting from the original ARM CPU-optimized software, the Cascade programmable coprocessor executes MP3 decoding at a clock frequency of only 6.5 MHz when subsequently implemented in Fujitsu’s ASIC process, while the real-time FPGA implementation supports efficient in-system verification. The same coprocessor can be reprogrammed to execute an AAC algorithm at even lower frequencies.

See CriticalBlue in booth #7360 at the 44th Design Automation Conference (DAC) in San Diego, June 4-8, 2007. Visit www.criticalblue.com/contactUs/register.php to arrange a demonstration.

About CriticalBlue
CriticalBlue’s Cascade accelerates embedded software by generating programmable, application-optimized coprocessors for implementation in SoCs, FPGAs and structured ASICs. Cascade accepts application binaries as input, allowing code to be accelerated without modification, while fitting naturally into the established software development flow. With Cascade, your product's core value remains in software. For more information, visit www.criticalblue.com.

Synopsys and DesignWare are registered trademarks of Synopsys, Inc. ARM, AMBA, ARM9 are trademarks or registered trademarks of ARM Limited. All other product or company names mentioned in this release are the property of their respective holders. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.