Lattice Releases ispLEVER Classic Design Tool Suite

- New FPGA / PLD Tool Set Targets High Volume, Mature Lattice Devices -

HILLSBORO, OR - April 24, 2007 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today released its new ispLEVER( Classic design software. This comprehensive software design tool suite supports all mature Lattice programmable devices including its GAL( and ispGAL( Simple PLDs (SPLDs); ispLSI(, MACH(, ispMACH( and ispXPLD( Complex PLDs (CPLDs); ORCA(, FPSC and ispXPGA( Field Programmable Gate Arrays (FPGAs); ispGDX( and ispGDX2(crosspoint devices. A Windows-based version of the new software package is available for download and license at no charge on the Lattice website (http://www.latticesemi.com/).

"The ispLEVER Classic design environment, based on Version 6.1 of our ispLEVER software design tool suite, is the result of over a thousand man-years of development effort," said Chris Fanning, corporate vice president of software and IP solutions at Lattice. "This Classic software design package will provide stable and continuing support for our older, high volume silicon products, even as we continue to develop the system-on-chip design capabilities in our standard software suite that are needed to support 65nm FPGAs and beyond."

"The reprogrammable nature of our products makes the need for long term design support imperative," said Stan Kopec, corporate vice president of marketing at Lattice. "Lattice is committed to providing accessible, quality design support for our silicon devices throughout their life cycle. Our ispLEVER Classic design tools will ensure our customers can continue to generate and update designs for these established device families."

The ispLEVER Classic design software is based on the complete ispLEVER software design tool suite, a comprehensive design environment for all Lattice programmable logic products. It includes a powerful set of software tools for all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis, in-system logic analysis and much more. The ispLEVER Classic design software includes everything necessary to take a project from concept through to a programmed device. Lattice also works closely with industry leaders Mentor Graphics(r) and Synplicity(r) to provide superior HDL synthesis and simulation solutions, fully integrated into the ispLEVER design flow.

Availability
Lattice's Windows-based ispLEVER Classic design tool suite is available for download now at no charge from the Lattice website. UNIX and Linux versions of ispLEVER Classic design software on hard media will be available directly from Lattice. The downloadable Windows version consists of 5 modules. These include:
* Primary Module (Supporting CPLD, SPLD products)
* FPGA Module
* Precision( RTL Synthesis Module (from Lattice's partner Mentor Graphics)
* Synplify( for Lattice Synthesis Module (from Lattice's partner Synplicity)
* ispLEVER Classic Help and Documentation Module
For user convenience, ispLEVER Classic also will be included on CD-ROM with future releases of Lattice's ispLEVER design tools. In the future, these standard ispLEVER software packages will provide support for all currently available Lattice 130nm and 90nm devices, including the LatticeEC(, LatticeECP(, LatticeXP(, LatticeECP2(, LatticeECP2M(, LatticeSC( and MachXO( device families.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.

Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party silicon suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), GAL, ispGAL, ispGDX, ispGDX2, ispLEVER, ispLSI, ispXPGA, ispXPLD, MACH, ORCA, ispMACH, LatticeEC, LatticeECP, LatticeXP, LatticeECP2, LatticeECP2M, LatticeSC, MachXO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders