BusinessWire
February 21, 2006 05:01 AM US Pacific Timezone

Tensilica Introduces Industry's Lowest Power Embedded Controller Cores; New Diamond Standard Family Members Deliver Unbeatable Combination of High Performance at Low Power

SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 21, 2006--Tensilica(R), Inc. today introduced the Diamond Standard family of synthesizable processor cores, which includes two synthesizable microcontroller CPUs optimized for area, performance and power efficiency. Competing directly with the ARM7 and ARM9 families of controllers, Tensilica's Diamond 108Mini and 212GP require significantly lower power and provide much higher performance, making them ideal for microcontroller and system controller slots. With a lower starting price point, lower average royalty rate, and a solid group of ASIC and foundry distribution partners, Tensilica expects to rapidly gain market share in the entry-level and medium-range controller segment.

"Our customers have requested power-efficient, off-the-shelf controllers based on the proven Xtensa architecture, and the Diamond Standard products are the result of the input we gathered from these customers," stated Steve Roddy, Tensilica's vice president of marketing. "We're proud that these processors far outperform their ARM equivalent synthesizable cores."

Based on Proven Xtensa ISA

The entire Diamond Standard family is based on Tensilica's proven Xtensa processor architecture, which is poised to become the number two licensable processor core architecture in the market based on 2006 volume shipments. The Xtensa architecture is a post-RISC-style architecture with native 32-bit data types (operands and ALUs) for the baseline 80+ instructions. Compact 24-bit/16-bit instruction encodings and the ability to do modeless switching between them reduces power consumption and produces 25 to 50 percent higher code density than standard 32-bit architectures. Register windows for efficient procedure switches provide high performance with low power. The base Xtensa ISA also provides powerful branch instructions and complex bit manipulations.

The Diamond 108Mini

The Diamond 108Mini is an ultra-low power, cacheless RISC controller with a rich interrupt architecture, a small gate count and the ability to attach local memory instruction and data RAMs of varying sizes. With a maximum operating clock frequency of 350 MHz in a 130 nm "LV type" process the Diamond 108Mini delivers ARM9 performance with lower power than the ARM7.

ARM 7TDMI-S Diamond ARM 968E-S
108Mini
Max Frequency (0.13u G) worst
case, optimized for speed 146 MHz 233-250 MHz 240 MHz
Dhrystone MIPS 131 300 264
Power - mW per MHz (0.13u G)
under typical conditions 0.11 0.11 0.12-0.23
Area 0.32 mm-2 0.46 mm-2 0.59 mm-2
# Interrupts 3 15 3
Timers No Yes No
Direct interface ports/wires No 32-bit input No
ports, 32-
bit output
ports

(Note: ARM specifications taken from ARM's public website.)

The Diamond 212GP

The Diamond 212GP is a flexible mid-range RISC controller that includes instruction and data caches, a 16-bit multiply-accumulator, DSP functions and zero-overhead loop support. The Diamond 212GP also includes a single-cycle latency local interface bus. This processor core provides 40 percent better performance and 30 percent lower power than an ARM9 processor.

ARM 946E-S Diamond 212GP
Max Frequency (0.13u G) worst
case, optimized for speed 210 MHz 230-250 MHz
Dhrystone MIPS 231 345
Power - mW per MHz (0.13u G)
typical conditions 0.30 0.195
Area 1.96 mm-2 0.70 mm-2
Zero-overhead looping No Yes
# Interrupts 3 15
Timers No Yes
Direct interface power/wires No 32-bit input
ports, 32-bit
output ports

Microcontroller-Style Direct Input Wires and Output Ports Simplify I/O

The Diamond 108Mini and Diamond 212GP provide designers with direct interface input ports and output wires for direct connections to other hardware blocks on the chip. These direct interface ports and wires provide a convenient and lower-power alternative compared to using bus-based, memory-mapped I/O interfaces. Thirty-two individually sampled input ports and 32 single-bit output wires provide device-driver programmers with a generous number of general-purpose I/O bits for hardware interface and system control. These I/O ports provide direct control between the Diamond processor and related peripherals. These wires and ports are similar in concept to GPIO pins on classic microcontrollers, and are unavailable on the ARM7 and ARM9 processors.

AMBA AHB Interface Available

All Tensilica Diamond Series cores are available with either the native high-performance Tensilica PIF processor interface, suitable for bridging to any on-chip bus (e.g. OCP, CoreConnect) or with an AMBA AHB-Lite interface. SOC designers therefore can choose any common on-chip bus and leverage existing infrastructure and peripheral component sets.

Pricing and Availability

Tensilica's new Diamond Standard family of processors is available now either direct from Tensilica, or from a roster of ASIC and foundry partners also announced today. See separate news release, or go to www.tensilica.com for more information. Pricing starts at $75,000 for the Diamond 108Mini for a single-use license with 5 cent per core royalties.

About Tensilica

Tensilica offers the broadest line of processor cores on the market today, with the six new members of the Diamond Standard processor family plus an infinite number of Xtensa configurable processor possibilities for customers requiring optimized, application-specific solutions. Tensilica's low-power, benchmark-proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. Tensilica also provides industry leading automated tool support for its processor families. For more information, visit www.tensilica.com.