BusinessWire
October 19, 2005 10:00 AM US Pacific Timezone

AccelChip to Showcase IP-Explorer Technology at GSPx; Paper to Be Presented on QRD-RLS Adaptive Filtering in Beamforming Applications

MILPITAS, Calif.--(BUSINESS WIRE)--Oct. 19, 2005--AccelChip Inc., the industry's leading provider of semiconductor Intellectual Property (IP) and software for MATLAB(R) and Simulink(R) DSP algorithms targeting FPGAs and ASICs, will be demonstrating its new IP-Explorer(TM) Technology at GSPx in Santa Clara, California next week in booth #200.

IP-Explorer Technology is now included within AccelChip's DSP Synthesis version 2005.4. The new technology extends the product's ability to rapidly explore the possible design space for DSP algorithms by automating macro and micro-architecture tradeoffs of key DSP building blocks. The result is an algorithmic synthesis solution with unparalleled automation and quality of results.

The company is also presenting a paper titled, "Efficient Methodology for Implementation of Matrix Inversion in Fixed-Point Hardware," on Tuesday, October 25 at 2:30 pm. Ramon Uribe of AccelChip will be providing a technical overview of an implementation of QRD-RLS adaptive filtering in beamforming applications. The paper will also be available on the AccelChip website immediately following the conference. Please visit www.accelchip.com/papers.html for more information.

In addition to AccelChip DSP Synthesis with IP-Explorer technology, the company will be showcasing the newest linear algebra DSP IP cores generators recently added to the popular AccelWare(R) Advanced Math Toolkit. These unique generators can be used in the deployment of adaptive signal processing filter algorithms commonly found in wireless solutions such as smart antenna beamforming applications and MIMO-OFDM wireless LAN design.

About GSPx

GSPx will be held at the Santa Clara, California Convention Center from Monday, October 24 through Thursday, October 27. For more information about the conference or to register for the event, please visit www.gspx.com.

About the Company

AccelChip Inc. is the industry's only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip's proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com. For more information, contact Wendy Truax at (503) 351-0103 or by email at wendy@hipcom.com

AccelChip, IP-Explorer and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.