BusinessWire
October 10, 2005 10:49 AM US Pacific Timezone

AccelChip Broadens Linear Algebra Intellectual Property Offering; See the New IP Generators at the GSPx Conference October 24-27

The new AccelWare generators include a QR Decomposition-RLS Spatial Filter which is based on a recursive least squares (RLS) approximation, a Givens Array Rotation, which rotates the elements of an array by a specified angle, and a Triangular Matrix Inverse generator which builds logic that returns the inverse for an upper- or lower-triangular input matrix. Adaptive signal processing algorithms that use RLS are found in numerous applications such as equalization, beamforming and adaptive filtering.

"QRD-RLS adaptive filters are being hand-designed by companies around the globe" said Michael Bohm, CTO and vice president of product development, AccelChip Inc. "The advantage of using QR decomposition in an RLS algorithm is that it's a highly robust algorithm, less computationally expensive than performing an explicit matrix inversion and more numerically accurate. By providing it as an AccelWare generator, customers take advantage of our Model-Based Design flow, augmenting the simulation-only model provided by The MathWorks with an implementation model."

As of the 2005.4 release, AccelChip now has matrix inversion and factorization AccelWare core generators that support QRD-RLS Spatial Filters, QR matrix factorization and inversion, Singular Value Decomposition, Cholesky factorization and inversion, and triangular matrix inversion.

In addition to the new AccelWare generators, enhancements have been added to the AccelWare Building Blocks and Signal Processing toolkits providing additional macro-architectures including an new streaming Radix-4, FFT/IFFT generator that is capable of running over 100 MHz on a Xilinx Virtex-4 device.

QRD-RLS Adaptive Filtering in Beamforming Applications

AccelChip will be providing a technical overview of an implementation of QRD-RLS adaptive filtering in beamforming applications at the GSPx Conference October 24-27 in Santa Clara, California. Ramon Uribe and Dr. Tom Cesear of AccelChip will present their paper, Efficient Methodology for Implementation of Matrix Inversion in Fixed-Point Hardware. This paper will also be available on the AccelChip website immediately following the conference.

Pricing and Availability

Version 2005.4 of AccelWare IP Toolkits and of AccelChip DSP Synthesis is now shipping. Current AccelChip customers on maintenance agreements will receive the new release at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email sales@accelchip.com. AccelWare toolkits start at $5000 for a toolkit of DSP Core Generators.

About the Company

AccelChip Inc. is the industry's only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip's proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com. For more information, contact Wendy Truax at 503-351-0103 or by email at wendy@hipcom.com

AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.