ESC Round One
Cool and Groovy Galore

The barrage of Embedded Systems Conference announcements has officially begun. Here at the first day of the show, we wanted to wade through the vast wasteland of “Company A standardizes on Company B’s products” and “Company C Announces Essentially Nothing at This Year’s ESC” to bring you a few really interesting developments.

As we mentioned last week, two of the key themes of ESC this year will be multi-core and ESL. From first-day announcements, let’s discuss a few of our favorites in each category. On the multi-core side, we’ll look at Virtutech’s announcement of Simics support for Freescale’s MPC8641D dual-core processor. Many developers are skeptical about the use of simulation for software debug when actual hardware is often available, but a simulation-based methodology offers some compelling advantages, particularly with the move to multi-core.

Also, while we don’t subscribe to the hype surrounding the “ESL” terminology, we wholeheartedly endorse many of the tools and methodologies that fall into that ill-formed bucket. In that spirit, we want to talk about Altium and Altera, (no, we’re not just starting our coverage with the As) who both announced new C-to-FPGA SW/HW compilers at this year’s ESC.

Virtutech started the show with two announcements on their Simics software simulation environment. The first is support for Freescale’s new MPC8641D dual-core processor. While simulation-based debug has been struggling to gain mindshare with embedded development teams, its use in multi-core applications promises to amplify the advantages considerably. With a more traditional processor, simulation-based debug allows some embedded debug features not easily duplicated with normal, hardware-based methodology. Failure mechanisms that are difficult to create in actual hardware are a snap with simulation, and other techniques like backward execution can offer valuable insight in locating tricky bugs.

With multi-core, however, the indeterminate execution of threads on asynchronous processing units creates a number of sneaky failure mechanisms that might not show up in a typical hardware debug scenario. With simulation, it is straightforward to run multiple passes with large variations in clock frequency, for example, to root out conditions where unanticipated timing problems can cause nasty behaviors.

Simulation also offers the obvious advantage of debug and development before actual hardware platforms are available, or available in sufficient quantities to support the entire development team. Even where prototype hardware is sometimes ready, it is typically operating in pre-production mode, making it unreliable and creating a situation where it can be difficult to tell if problems are caused by software bugs or by immature hardware prototypes. Developing and debugging in a simulation environment sidesteps many of these issues.

Emphasizing the utility of their approach, Virtutech is also announcing that Wind River is using Simics for development of board support packages. Winning over a major embedded development powerhouse like Wind River is not only a clear commercial success for Virtutech, it is a strong endorsement of the simulation-based methodology. As a primary supplier of OS, tools, and IP for embedded development, Wind River typically encounters the tough technical challenges before their customers do, and their methodology decisions could be a leading indicator of where embedded development is heading.

On the somewhat controversial ESL front, there are interesting and very similar announcements from both Altera and Altium. Each company is announcing a C-to-hardware compilation capability for their FPGA development tool suites. In Altera’s case, they are touting their new C-to-hardware compiler (C2H) that complements their Nios II development kit and their SOPC Builder tool suite. Altera’s new compiler (see our related article in FPGA Journal this week) allows you to select a normal C function from your embedded software and compile it directly into hardware. C2H creates a hardware accelerator and connects it automatically to your Nios II processor-based application, dramatically improving performance (with up to 40X application speedup reported by customers) and typically reducing overall power consumption in the process.

While FPGA-based processor cores are not known for their stellar performance, the ability to automatically accelerate to hardware alleviates much of that issue, allowing the less performance-critical control functions to be executed on the soft-core processor, while data-crunching is massively accelerated by highly parallelized hardware datapaths.

Taking a similar approach is Altium, who is announcing a C-to-FPGA hardware addition to their Altium Designer FPGA development suite. Perhaps the most important distinction between Altium and Altera at the top level is Altium’s vendor and technology independence. While Altera’s tool is focused exclusively on customers using Altera’s FPGAs and their Nios II embedded processor core, Altium has always been vendor neutral. Altium offers a complete design flow from FPGA to board that is independent of any particular FPGA technology. Even their development boards allow several vendors’ FPGAs to be swapped in and out, enabling a very portable design methodology.

The addition of this C-to-hardware compilation capability to the Altium Designer suite extends that flexibility beyond silicon vendor neutrality, allowing easy alteration of the hardware/software partition in design functionality. This software/hardware neutrality, along with Altium’s vendor-agnostic FPGA hardware development, create a situation where critical design decisions affecting cost, power, and performance can be left until the last minute and changed quickly in response to moving requirements or availability of new technologies. Development teams can then be more nimble in their design process and get better products to market more quickly with lower risk.

All of these C-to-hardware technologies are rather new and will likely take time to mature, but they offer significant promise in their ability to blur the line between functionality that must be delivered in hardware to meet performance and power goals and functionality that must be created in software for flexibility and hardware efficiency. With these technologies, embedded systems-on-chip become more practical on platforms like FPGAs, and more capable and flexible embedded system designs will result.

ESC clearly has a lot more in store for us, as the show floor hasn’t even opened yet. We’ll be out there for you, however, scouring the show and the briefing rooms, learning the latest on embedded technology trends and techniques (and maybe hitting a party or two in the process). Stay tuned for our next update.

Kevin Morris, Embedded Technology Journal

April 4, 2006

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